IP PortfolioSensing and RF

Sensing and RF: radar, LiDAR, infrared, wireless

Radar (FMCW, pulse, MIMO) processing, LiDAR (ToF, FMCW) front ends and DSP, infrared and thermal imaging readout, RF transceiver and baseband blocks, GNSS, ultra-wideband and III-V RF front ends.

Blocks 130Implemented 10Families 12III-V process 23 · ASIC (CMOS) only 30 · FPGA + ASIC 77

radar 24 lidar 13 infrared 10 rf_frontend 12 iii_v_rf 9 wireless_baseband 28 gnss 5 rfid_nfc 5 sonar_ultrasound 5 ew_sigint 5 time_frequency 4 rf_front_end 10

radar

24 blocks · 7 implemented

ID	Block	Maturity	Targets	Difficulty
of_radar_fmcw_chirp_ctrl	FMCW chirp sequencer	simulated	FPGA + ASIC	Medium
of_radar_fe_24g	24 GHz radar transceiver front end	planned	ASIC (CMOS) only	Very hard
of_radar_fe_60g	60 GHz radar transceiver front end	planned	ASIC (CMOS) only	Very hard
of_radar_fe_77g	76 to 81 GHz automotive radar front end	planned	ASIC (CMOS) only	Very hard
of_radar_adc_frontend_dig	Radar IF digital front end	simulated	FPGA + ASIC	Medium
of_radar_range_fft	Range FFT engine	simulated	FPGA + ASIC	Medium
of_radar_doppler_fft	Doppler FFT engine	simulated	FPGA + ASIC	Medium
of_radar_cfar	CFAR detector (CA, OS, GO, SO)	simulated	FPGA + ASIC	Medium
of_radar_doa_bf	Direction-of-arrival beamforming estimator	planned	FPGA + ASIC	Hard
of_radar_doa_subspace	Subspace DOA engine (MUSIC, ESPRIT)	planned	FPGA + ASIC	Very hard
of_radar_mimo_va	MIMO virtual array processor	planned	FPGA + ASIC	Hard
of_radar_pointcloud	Radar point cloud generator	simulated	FPGA + ASIC	Easy
of_radar_tracker	Multi-target Kalman tracker	planned	FPGA + ASIC	Hard
of_radar_clustering	Point cloud clustering engine	planned	FPGA + ASIC	Hard
of_radar_imaging_4d	4D imaging radar processor	planned	FPGA + ASIC	Very hard
of_radar_sar	Synthetic aperture radar processor	planned	FPGA + ASIC	Very hard
of_radar_gpr	Ground-penetrating radar processor	planned	FPGA + ASIC	Hard
of_radar_pulse_doppler	Pulse-Doppler radar processor	planned	FPGA + ASIC	Hard
of_radar_interference	Radar interference mitigation	planned	FPGA + ASIC	Hard
of_radar_vital_signs	Radar vital sign extraction	planned	FPGA + ASIC	Medium
of_radar_phased_array_ctrl	Phased array beam steering controller	simulated	FPGA + ASIC	Medium
of_radar_bf_ic	Analog phased array beamformer core	planned	ASIC (CMOS) only	Very hard
of_radar_bf_digital	Digital beamformer	planned	FPGA + ASIC	Hard
of_radar_calib	Radar channel calibration engine	planned	FPGA + ASIC	Medium

lidar

13 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_lidar_tdc_tof	Pulsed ToF multi-hit TDC	planned	ASIC (CMOS) only	Hard
of_lidar_spad_readout	SPAD array readout	planned	ASIC (CMOS) only	Very hard
of_lidar_histogram	Time-correlated histogramming engine	simulated	FPGA + ASIC	Medium
of_lidar_fmcw_lin	FMCW LiDAR chirp linearisation	planned	FPGA + ASIC	Hard
of_lidar_fmcw_proc	FMCW LiDAR beat processor	planned	FPGA + ASIC	Hard
of_lidar_laser_drv_905	905 nm pulsed laser driver	planned	ASIC (CMOS) only	Hard
of_lidar_laser_drv_1550	1550 nm laser and amplifier driver	planned	ASIC (CMOS) only	Hard
of_lidar_apd_afe	APD receiver front end	planned	ASIC (CMOS) only	Hard
of_lidar_mems_mirror_drv	MEMS mirror driver	planned	ASIC (CMOS) only	Hard
of_lidar_pc_proc	LiDAR point cloud processor	planned	FPGA + ASIC	Medium
of_lidar_opa_ctrl	Optical phased array controller	planned	FPGA + ASIC	Hard
of_lidar_iiiv_swir_spad	InGaAs/InP SPAD for 1550 nm	planned	III-V process	Very hard
of_lidar_iiiv_vcsel_array	GaAs VCSEL array with addressable drive	planned	III-V process	Very hard

infrared

10 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_ir_bolometer_roic	Microbolometer ROIC	planned	ASIC (CMOS) only	Very hard
of_ir_ingaas_swir_roic	InGaAs SWIR ROIC	planned	ASIC (CMOS) only	Very hard
of_ir_mwir_lwir_roic	MWIR/LWIR cooled ROIC	planned	ASIC (CMOS) only	Very hard
of_ir_iiiv_ingaas_fpa	InGaAs photodiode focal plane array	planned	III-V process	Very hard
of_ir_iiiv_t2sl_fpa	Type-II superlattice infrared detector array	planned	III-V process	Very hard
of_ir_nuc	Non-uniformity correction engine	simulated	FPGA + ASIC	Medium
of_ir_thermal_isp	Thermal image processor	planned	FPGA + ASIC	Medium
of_ir_radiometry	Radiometric temperature engine	planned	FPGA + ASIC	Medium
of_ir_gas_ndir	NDIR gas detection processor	planned	ASIC (CMOS) only	Medium
of_ir_ogi	Optical gas imaging processor	planned	FPGA + ASIC	Hard

rf_frontend

12 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_rf_lna	Low-noise amplifier family	planned	ASIC (CMOS) only	Hard
of_rf_pa	CMOS power amplifier	planned	ASIC (CMOS) only	Hard
of_rf_mixer	Mixer family	planned	ASIC (CMOS) only	Medium
of_rf_synth	RF frequency synthesizer	planned	ASIC (CMOS) only	Very hard
of_rf_switch	RF switch (SPDT to SP8T)	planned	ASIC (CMOS) only	Medium
of_rf_phase_shifter	Digital phase shifter	planned	ASIC (CMOS) only	Hard
of_rf_attenuator	Digital step attenuator	planned	ASIC (CMOS) only	Medium
of_rf_vga	RF variable gain amplifier	planned	ASIC (CMOS) only	Medium
of_rf_power_detector	RF power detector	planned	ASIC (CMOS) only	Medium
of_rf_balun_match	Integrated balun and matching network library	planned	ASIC (CMOS) only	Medium
of_rf_lo_dist	LO distribution and quadrature generator	planned	ASIC (CMOS) only	Medium
of_rf_frontend_ctrl	RF front end control interface	planned	FPGA + ASIC	Easy

iii_v_rf

9 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_rf_gaas_phemt_lna	GaAs pHEMT LNA	planned	III-V process	Hard
of_rf_gaas_phemt_pa	GaAs pHEMT power amplifier	planned	III-V process	Very hard
of_rf_gaas_hbt_pa	GaAs HBT handset power amplifier	planned	III-V process	Very hard
of_rf_gaas_switch	GaAs pHEMT switch and attenuator	planned	III-V process	Hard
of_rf_gaas_mmic_mixer	GaAs MMIC mixer and multiplier	planned	III-V process	Hard
of_rf_gaas_core_chip	GaAs T/R core chip	planned	III-V process	Very hard
of_rf_inp_hbt_pa	InP HBT millimeter-wave and sub-THz PA	planned	III-V process	Very hard
of_rf_inp_hbt_lna	InP HEMT/HBT sub-THz LNA	planned	III-V process	Very hard
of_rf_inp_transceiver	InP sub-THz transceiver front end	planned	III-V process	Very hard

wireless_baseband

28 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_wl_nr_ofdm_mod	5G NR OFDM modulator	planned	FPGA + ASIC	Hard
of_wl_nr_ofdm_demod	5G NR OFDM demodulator	planned	FPGA + ASIC	Hard
of_wl_nr_chest	5G NR channel estimator	planned	FPGA + ASIC	Hard
of_wl_mimo_detector	MIMO detector	planned	FPGA + ASIC	Very hard
of_wl_nr_beam_mgmt	5G NR beam management engine	planned	FPGA + ASIC	Hard
of_wl_nr_prach	5G NR PRACH detector	planned	FPGA + ASIC	Hard
of_wl_nr_precoder	5G NR layer mapper and precoder	planned	FPGA + ASIC	Medium
of_wl_lte_phy	LTE PHY baseband	planned	FPGA + ASIC	Very hard
of_wl_nbiot_phy	NB-IoT and LTE-M PHY	planned	FPGA + ASIC	Hard
of_wl_wifi6_bb	Wi-Fi 6 baseband	planned	FPGA + ASIC	Very hard
of_wl_wifi7_bb	Wi-Fi 7 baseband extensions	planned	FPGA + ASIC	Very hard
of_wl_wifi_halow_bb	Wi-Fi HaLow baseband	planned	FPGA + ASIC	Hard
of_wl_ble_phy	Bluetooth Low Energy PHY	planned	FPGA + ASIC	Medium
of_wl_802154_phy	IEEE 802.15.4 O-QPSK PHY	planned	FPGA + ASIC	Medium
of_wl_uwb_phy	UWB HRP PHY with secure ranging	planned	FPGA + ASIC	Very hard
of_wl_css_modem	Chirp spread spectrum modem	planned	FPGA + ASIC	Medium
of_wl_subghz_fsk	Sub-GHz FSK/GFSK modem	planned	FPGA + ASIC	Medium
of_wl_dvbs2x_demod	DVB-S2X demodulator	planned	FPGA + ASIC	Very hard
of_wl_dvbs2x_mod	DVB-S2X modulator	planned	FPGA + ASIC	Hard
of_wl_ccsds_modem	CCSDS space link modem	planned	FPGA + ASIC	Hard
of_wl_ddc	Digital down converter	simulated	FPGA + ASIC	Medium
of_wl_duc	Digital up converter	planned	FPGA + ASIC	Medium
of_wl_dpd	Digital predistortion engine	planned	FPGA + ASIC	Very hard
of_wl_cfr	Crest factor reduction	planned	FPGA + ASIC	Hard
of_wl_channelizer	Polyphase filter bank channelizer	planned	FPGA + ASIC	Hard
of_wl_agc	Digital automatic gain control	planned	FPGA + ASIC	Easy
of_wl_iq_corr	IQ imbalance and DC offset corrector	planned	FPGA + ASIC	Medium
of_wl_fronthaul_framer	Radio fronthaul framer	planned	FPGA + ASIC	Hard

gnss

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_gnss_acq	GNSS acquisition engine	planned	FPGA + ASIC	Hard
of_gnss_track	GNSS tracking correlator bank	planned	FPGA + ASIC	Hard
of_gnss_l5_e5	GNSS L5/E5 dual-frequency extension	planned	FPGA + ASIC	Hard
of_gnss_rf_fe	GNSS RF front end	planned	ASIC (CMOS) only	Very hard
of_gnss_interference	GNSS interference and spoofing monitor	planned	FPGA + ASIC	Hard

rfid_nfc

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_rf_harvester	RF energy harvesting rectifier	planned	ASIC (CMOS) only	Hard
of_rf_uhf_rfid_tag	UHF RFID tag front end and protocol	planned	ASIC (CMOS) only	Hard
of_rf_uhf_rfid_reader	UHF RFID reader baseband	planned	FPGA + ASIC	Medium
of_rf_nfc_fe	NFC analog front end	planned	ASIC (CMOS) only	Hard
of_rf_nfc_proto	NFC protocol controller	planned	FPGA + ASIC	Medium

sonar_ultrasound

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sonar_bf	Sonar and ultrasound receive beamformer	planned	FPGA + ASIC	Hard
of_sonar_tx_bf	Ultrasound transmit beamformer	planned	FPGA + ASIC	Medium
of_sonar_bmode	Ultrasound B-mode processor	planned	FPGA + ASIC	Medium
of_sonar_doppler	Ultrasound Doppler processor	planned	FPGA + ASIC	Hard
of_sonar_active	Active sonar signal processor	planned	FPGA + ASIC	Hard

ew_sigint

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_ew_wb_channelizer	Wideband EW channelizer	planned	FPGA + ASIC	Very hard
of_ew_pdw_gen	Pulse descriptor word generator	planned	FPGA + ASIC	Hard
of_ew_deinterleaver	Pulse deinterleaver	planned	FPGA + ASIC	Hard
of_ew_df	Direction finding processor	planned	FPGA + ASIC	Hard
of_ew_spectrum_monitor	Real-time spectrum monitor	planned	FPGA + ASIC	Medium

time_frequency

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_time_ptp_gm	IEEE 1588 PTP grandmaster timing core	planned	FPGA + ASIC	Hard
of_time_atomic_iface	Atomic clock disciplining interface	planned	FPGA + ASIC	Hard
of_time_csac_ctrl	Chip-scale atomic clock control loop	planned	ASIC (CMOS) only	Very hard
of_time_synce	SyncE and frequency synchronizer	planned	FPGA + ASIC	Hard

rf_front_end

10 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_rf_gaas_limiter	GaAs Schottky/PIN receiver limiter	planned	III-V process	Medium
of_rf_iiiv_ipd_couplers	III-V integrated passive coupler and filter set	planned	III-V process	Medium
of_rf_iiiv_detector	III-V RF power and log detector	planned	III-V process	Medium
of_rf_gaas_twa	GaAs distributed (traveling-wave) amplifier	planned	III-V process	Hard
of_rf_gaas_doherty	GaAs Doherty power amplifier	planned	III-V process	Hard
of_rf_gaas_ka_satcom_fe	GaAs Ka-band satcom transmit and receive chains	planned	III-V process	Hard
of_rf_gaas_fr2_repeater	GaAs 5G FR2 repeater gain chain	planned	III-V process	Hard
of_rf_iiiv_phase_shifter	III-V digital phase shifter and vector modulator	planned	III-V process	Hard
of_rf_iiiv_ttd	III-V true-time-delay MMIC	planned	III-V process	Hard
of_iiiv_freq_multiplier_chain	III-V frequency multiplier chain to D-band and 300 GHz	planned	III-V process	Very hard

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