IP PortfolioSensing and RFlidar
of_lidar_fmcw_proc
FMCW LiDAR beat processor
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Range and velocity extraction from up and down chirp beat spectra with FFT, peak interpolation and Doppler disambiguation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| beat | in | AXI4-Stream | 32 | |
| points | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in lidar
| ID | Block | Maturity |
|---|---|---|
| of_lidar_tdc_tof | Pulsed ToF multi-hit TDC | planned |
| of_lidar_spad_readout | SPAD array readout | planned |
| of_lidar_histogram | Time-correlated histogramming engine | simulated |
| of_lidar_fmcw_lin | FMCW LiDAR chirp linearisation | planned |
| of_lidar_laser_drv_905 | 905 nm pulsed laser driver | planned |
| of_lidar_laser_drv_1550 | 1550 nm laser and amplifier driver | planned |
| of_lidar_apd_afe | APD receiver front end | planned |
| of_lidar_mems_mirror_drv | MEMS mirror driver | planned |
| of_lidar_pc_proc | LiDAR point cloud processor | planned |
| of_lidar_opa_ctrl | Optical phased array controller | planned |