IP PortfolioSensing and RFradar
of_radar_adc_frontend_dig
Radar IF digital front end
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Per-channel decimation, DC removal, IQ imbalance correction and chirp-aligned sample framing between the radar ADCs and the range FFT.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| adc_in | in | AXI4-Stream | 64 | |
| samples | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in radar
| ID | Block | Maturity |
|---|---|---|
| of_radar_fmcw_chirp_ctrl | FMCW chirp sequencer | simulated |
| of_radar_fe_24g | 24 GHz radar transceiver front end | planned |
| of_radar_fe_60g | 60 GHz radar transceiver front end | planned |
| of_radar_fe_77g | 76 to 81 GHz automotive radar front end | planned |
| of_radar_range_fft | Range FFT engine | simulated |
| of_radar_doppler_fft | Doppler FFT engine | simulated |
| of_radar_cfar | CFAR detector (CA, OS, GO, SO) | simulated |
| of_radar_doa_bf | Direction-of-arrival beamforming estimator | planned |
| of_radar_doa_subspace | Subspace DOA engine (MUSIC, ESPRIT) | planned |
| of_radar_mimo_va | MIMO virtual array processor | planned |