IP PortfolioSoC interconnectamba interconnect
of_axi4_reg_slice
AXI4 register slice
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Per-channel AXI4 pipeline register (full, forward or reverse) for timing closure on long routes, full throughput.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_axi | in | valid-qualified bus | 256 | AXI4 slave port (AW/W/AR channels) |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- AMBA AXI4
Basis projects
Permissive open projects the implementation may build on.
- PULP AXI (SHL-0.51)
- verilog-axi (MIT)
More in amba interconnect
| ID | Block | Maturity |
|---|---|---|
| of_axil_xbar | AXI4-Lite crossbar | fpga-routed |
| of_axis_arb | AXI4-Stream packet arbiter / mux | simulated |
| of_axis_fifo | AXI4-Stream FIFO | simulated |
| of_axis_reg_slice | AXI4-Stream register slice | simulated |
| of_axis_width_conv | AXI4-Stream width converter | simulated |
| of_axi4_xbar | AXI4 crossbar | simulated |
| of_axi4_width_conv | AXI4 data-width converter | simulated |
| of_axi4_id_remap | AXI4 ID width converter | planned |
| of_axi4_burst_split | AXI4 burst splitter | planned |
| of_axi4_firewall | AXI4 firewall | simulated |