IP PortfolioSoC interconnect
System interconnect and SoC infrastructure
On-chip buses and crossbars, NoC, DMA, interrupt controllers, timers, clock/reset/power control, debug and trace, mailboxes, boot and system management.
Blocks 101Implemented 53Families 17FPGA + ASIC 101
amba interconnect 20bus bridges and converters 8wishbone, tilelink and obi 6register blocks 4clock domain crossing 5clock, reset and power control 8interrupt controllers 6timers 6network on chip 4dma 4inter-processor communication 2debug and trace 10system management 4memory system and caches 4access control and iommu 3monitoring and error reporting 4debug_and_test 3
amba interconnect
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_axil_xbar | AXI4-Lite crossbar | fpga-routed | FPGA + ASIC | Medium |
| of_axis_arb | AXI4-Stream packet arbiter / mux | simulated | FPGA + ASIC | Easy |
| of_axis_fifo | AXI4-Stream FIFO | simulated | FPGA + ASIC | Easy |
| of_axis_reg_slice | AXI4-Stream register slice | simulated | FPGA + ASIC | Easy |
| of_axis_width_conv | AXI4-Stream width converter | simulated | FPGA + ASIC | Easy |
| of_axi4_xbar | AXI4 crossbar | simulated | FPGA + ASIC | Hard |
| of_axi4_reg_slice | AXI4 register slice | simulated | FPGA + ASIC | Easy |
| of_axi4_width_conv | AXI4 data-width converter | simulated | FPGA + ASIC | Hard |
| of_axi4_id_remap | AXI4 ID width converter | planned | FPGA + ASIC | Medium |
| of_axi4_burst_split | AXI4 burst splitter | planned | FPGA + ASIC | Medium |
| of_axi4_firewall | AXI4 firewall | simulated | FPGA + ASIC | Medium |
| of_axi4_qos | AXI4 QoS regulator | planned | FPGA + ASIC | Medium |
| of_axi4_sram | AXI4 SRAM controller | simulated | FPGA + ASIC | Medium |
| of_axis_switch | AXI4-Stream switch | simulated | FPGA + ASIC | Medium |
| of_ahb_matrix | AHB multilayer matrix | planned | FPGA + ASIC | Medium |
| of_ahb_sram | AHB SRAM controller | planned | FPGA + ASIC | Easy |
| of_apb_splitter | APB decoder and splitter | simulated | FPGA + ASIC | Easy |
| of_ace_lite_bridge | ACE-Lite I/O coherency bridge | planned | FPGA + ASIC | Hard |
| of_chi_axi_bridge | CHI to AXI4 bridge | planned | FPGA + ASIC | Very hard |
| of_chi_mesh | CHI-style coherent mesh interconnect | planned | FPGA + ASIC | Very hard |
bus bridges and converters
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_ahb2apb | AHB-Lite to APB bridge | simulated | FPGA + ASIC | Easy |
| of_axi4_to_axil | AXI4 to AXI4-Lite converter | simulated | FPGA + ASIC | Easy |
| of_axil_to_apb | AXI4-Lite to APB bridge | simulated | FPGA + ASIC | Easy |
| of_axi4_to_ahb | AXI4 to AHB bridge | planned | FPGA + ASIC | Medium |
| of_ahb_to_axi4 | AHB to AXI4 bridge | planned | FPGA + ASIC | Medium |
| of_axi4_cdc | AXI4 clock-domain crossing bridge | simulated | FPGA + ASIC | Medium |
| of_apb_cdc | APB clock-domain crossing bridge | simulated | FPGA + ASIC | Easy |
| of_axi4_to_axis | AXI4 memory-mapped to stream bridge | planned | FPGA + ASIC | Easy |
wishbone, tilelink and obi
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_wb_ic | Wishbone B4 shared-bus interconnect | simulated | FPGA + ASIC | Medium |
| of_wb_xbar | Wishbone B4 pipelined crossbar | planned | FPGA + ASIC | Medium |
| of_wb_axil_bridge | Wishbone and AXI4-Lite bridges | planned | FPGA + ASIC | Easy |
| of_tlul_xbar | TileLink TL-UL crossbar | planned | FPGA + ASIC | Medium |
| of_tl_axi4_bridge | TileLink to AXI4 bridge | planned | FPGA + ASIC | Medium |
| of_obi_xbar | OBI crossbar and AXI4 bridge | planned | FPGA + ASIC | Medium |
register blocks
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_regbank | Register bank core (register-map driven) | simulated | FPGA + ASIC | Easy |
| of_apb_regs | APB slave register block | fpga-routed | FPGA + ASIC | Easy |
| of_axil_regs | AXI4-Lite slave register block | simulated | FPGA + ASIC | Easy |
| of_wb_regs | Wishbone B4 slave register block | simulated | FPGA + ASIC | Easy |
clock domain crossing
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_sync_bit | Multi-flop bit synchronizer | fpga-routed | FPGA + ASIC | Easy |
| of_sync_bus | Multi-bit bus synchronizer (handshake) | fpga-routed | FPGA + ASIC | Medium |
| of_sync_handshake | Four-phase req/ack handshake synchronizer | simulated | FPGA + ASIC | Medium |
| of_sync_pulse | Toggle pulse synchronizer | simulated | FPGA + ASIC | Easy |
| of_sync_reset | Reset synchronizer | simulated | FPGA + ASIC | Easy |
clock, reset and power control
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_clk_div | Integer clock divider (50 % duty) | fpga-routed | FPGA + ASIC | Easy |
| of_clk_gate | Clock-gating cell model (latch-based ICG) | simulated | FPGA + ASIC | Easy |
| of_clk_mux_gf | Glitch-free clock multiplexer | simulated | FPGA + ASIC | Medium |
| of_ccu | Clock control unit | simulated | FPGA + ASIC | Medium |
| of_rcu | Reset control unit | simulated | FPGA + ASIC | Easy |
| of_ppu | Power policy unit | simulated | FPGA + ASIC | Medium |
| of_clk_mon | Clock monitor and frequency meter | planned | FPGA + ASIC | Easy |
| of_dvfs_ctrl | DVFS controller | planned | FPGA + ASIC | Medium |
interrupt controllers
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_irq_agg | Interrupt aggregator | simulated | FPGA + ASIC | Easy |
| of_plic | RISC-V PLIC | simulated | FPGA + ASIC | Medium |
| of_clic | RISC-V CLIC | planned | FPGA + ASIC | Medium |
| of_aplic | RISC-V APLIC | planned | FPGA + ASIC | Hard |
| of_imsic | RISC-V IMSIC | planned | FPGA + ASIC | Hard |
| of_gic_style | GIC-style interrupt distributor | planned | FPGA + ASIC | Hard |
timers
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_timer | Programmable timer / counter with prescaler | fpga-routed | FPGA + ASIC | Easy |
| of_watchdog | Windowed watchdog timer | fpga-routed | FPGA + ASIC | Easy |
| of_aclint | RISC-V ACLINT | simulated | FPGA + ASIC | Easy |
| of_rtc | Real-time clock and calendar | planned | FPGA + ASIC | Easy |
| of_timestamp | Global timestamp generator | planned | FPGA + ASIC | Easy |
| of_timer_multi | Multi-channel general-purpose timer | planned | FPGA + ASIC | Easy |
network on chip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_noc_router | NoC router | simulated | FPGA + ASIC | Hard |
| of_noc_ni_axi | AXI4 NoC network interface | simulated | FPGA + ASIC | Hard |
| of_noc_gen | NoC topology generator | planned | FPGA + ASIC | Very hard |
| of_noc_link_cdc | NoC link pipeline and clock crossing | planned | FPGA + ASIC | Medium |
dma
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_dma_sg | Scatter-gather DMA controller | simulated | FPGA + ASIC | Hard |
| of_dma_nd | Multi-dimensional (2D/3D) DMA | planned | FPGA + ASIC | Hard |
| of_dma_stream | AXI4-Stream DMA (MM2S / S2MM) | simulated | FPGA + ASIC | Medium |
| of_dma_mcu | MCU peripheral DMA | planned | FPGA + ASIC | Medium |
inter-processor communication
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_mailbox | Inter-processor mailbox | simulated | FPGA + ASIC | Easy |
| of_hw_semaphore | Hardware semaphore bank | planned | FPGA + ASIC | Easy |
debug and trace
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_rv_dm | RISC-V Debug Module | simulated | FPGA + ASIC | Hard |
| of_rv_dtm | RISC-V JTAG debug transport module | fpga-routed | FPGA + ASIC | Medium |
| of_jtag_tap | IEEE 1149.1 TAP controller | fpga-routed | FPGA + ASIC | Easy |
| of_ijtag_net | IEEE 1687 IJTAG network | planned | FPGA + ASIC | Medium |
| of_rv_etrace | RISC-V E-Trace encoder | planned | FPGA + ASIC | Hard |
| of_rv_ntrace | RISC-V N-Trace encoder | planned | FPGA + ASIC | Hard |
| of_trace_funnel | Trace funnel, buffer and sink | planned | FPGA + ASIC | Medium |
| of_logic_analyzer | Integrated logic analyzer | simulated | FPGA + ASIC | Medium |
| of_jtag_axi | JTAG to AXI4 master bridge | planned | FPGA + ASIC | Medium |
| of_uart_bus_bridge | UART to bus debug bridge | planned | FPGA + ASIC | Easy |
system management
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_bootrom_ctrl | Boot ROM and boot-mode controller | simulated | FPGA + ASIC | Easy |
| of_sysctrl | System controller | simulated | FPGA + ASIC | Easy |
| of_pinmux | Pin multiplexer | simulated | FPGA + ASIC | Easy |
| of_addr_remap | Address remap unit | planned | FPGA + ASIC | Easy |
memory system and caches
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_l2_cache | Shared L2 cache controller | planned | FPGA + ASIC | Very hard |
| of_llc_dir | Last-level cache with coherence directory | planned | FPGA + ASIC | Very hard |
| of_ecc_scrubber | Memory ECC scrubber | planned | FPGA + ASIC | Easy |
| of_tcm_ctrl | Tightly coupled memory controller | planned | FPGA + ASIC | Easy |
access control and iommu
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_iommu | RISC-V IOMMU | planned | FPGA + ASIC | Very hard |
| of_iopmp | RISC-V IOPMP | planned | FPGA + ASIC | Medium |
| of_mpu_bus | Bus master memory protection unit | planned | FPGA + ASIC | Easy |
monitoring and error reporting
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_axi_perfmon | AXI4 performance monitor | planned | FPGA + ASIC | Medium |
| of_hpm_counters | Hardware event counter bank | planned | FPGA + ASIC | Easy |
| of_ras_reri | RAS error record unit (RERI) | planned | FPGA + ASIC | Medium |
| of_bus_timeout | Bus transaction timeout monitor | planned | FPGA + ASIC | Medium |
debug_and_test
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_mbist_march | March C- memory BIST controller | simulated | FPGA + ASIC | Medium |
| of_wrap_1500 | IEEE 1500 core test wrapper | simulated | FPGA + ASIC | Medium |
| of_jtag_tdr | JTAG user test data register | simulated | FPGA + ASIC | Easy |