AXI4 memory-mapped to stream bridge

Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2

Converts AXI4 write bursts to AXI4-Stream packets and AXI4-Stream packets into AXI4 read data, for FIFO-style memory-mapped access to streaming blocks.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
s_axi	in	valid-qualified bus	256	AXI4 slave port (AW/W/AR channels)
m_axis	out	AXI4-Stream	64
s_axis	in	AXI4-Stream	64

Standards

AMBA AXI4
AMBA AXI4-Stream

More in bus bridges and converters

ID	Block	Maturity
of_ahb2apb	AHB-Lite to APB bridge	simulated
of_axi4_to_axil	AXI4 to AXI4-Lite converter	simulated
of_axil_to_apb	AXI4-Lite to APB bridge	simulated
of_axi4_to_ahb	AXI4 to AHB bridge	planned
of_ahb_to_axi4	AHB to AXI4 bridge	planned
of_axi4_cdc	AXI4 clock-domain crossing bridge	simulated
of_apb_cdc	APB clock-domain crossing bridge	simulated