RISC-V IOMMU

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2

Input/output memory management unit with device context tables, Sv39/Sv48 two-stage translation, IOTLB, command and fault queues and MSI translation.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
s_axi	in	valid-qualified bus	256	AXI4 slave port (AW/W/AR channels)
m_axi	out	valid-qualified bus	256	AXI4 master port (AW/W/AR channels)

Standards

RISC-V IOMMU Architecture Specification 1.0

More in access control and iommu

ID	Block	Maturity
of_iopmp	RISC-V IOPMP	planned
of_mpu_bus	Bus master memory protection unit	planned