AMBA ACE bus functional model and agent

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3

ACE master agent with a cache model producing coherent transactions and snoop responses, plus an interconnect-side snoop generator.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
m_ace	out	valid-qualified bus	512
snoop	in	valid-qualified bus	128

Standards

AMBA ACE

More in amba bus vip

ID	Block	Maturity
of_vip_axi4_mon	AMBA AXI4 monitor and protocol checker	simulated
of_vip_axi4_bfm	AMBA AXI4 bus functional model and agent	simulated
of_vip_axil_mon	AMBA AXI4-Lite monitor and protocol checker	simulated
of_vip_axil_bfm	AMBA AXI4-Lite bus functional model and agent	simulated
of_vip_axis_mon	AMBA AXI4-Stream monitor and protocol checker	simulated
of_vip_axis_bfm	AMBA AXI4-Stream bus functional model and agent	simulated
of_vip_ahb_mon	AMBA AHB monitor and protocol checker	simulated
of_vip_ahb_bfm	AMBA AHB bus functional model and agent	simulated
of_vip_apb_mon	AMBA APB monitor and protocol checker	simulated
of_vip_apb_bfm	AMBA APB bus functional model and agent	simulated