IP PortfolioVerification IP
Verification IP
Protocol monitors, checkers, bus functional models, traffic generators and scoreboards for every interface and bus in the catalog, plus generic verification infrastructure.
Blocks 96Implemented 33Families 13FPGA + ASIC 96
amba bus vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_axi4_mon | AMBA AXI4 monitor and protocol checker | simulated | FPGA + ASIC | Medium |
| of_vip_axi4_bfm | AMBA AXI4 bus functional model and agent | simulated | FPGA + ASIC | Medium |
| of_vip_axil_mon | AMBA AXI4-Lite monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_axil_bfm | AMBA AXI4-Lite bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_axis_mon | AMBA AXI4-Stream monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_axis_bfm | AMBA AXI4-Stream bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_ahb_mon | AMBA AHB monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_ahb_bfm | AMBA AHB bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_apb_mon | AMBA APB monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_apb_bfm | AMBA APB bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_ace_mon | AMBA ACE monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_ace_bfm | AMBA ACE bus functional model and agent | planned | FPGA + ASIC | Hard |
| of_vip_chi_mon | AMBA CHI monitor and protocol checker | planned | FPGA + ASIC | Very hard |
| of_vip_chi_bfm | AMBA CHI bus functional model and agent | planned | FPGA + ASIC | Very hard |
serial peripheral vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_i2c_mon | I2C monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_i2c_bfm | I2C bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_i3c_mon | MIPI I3C monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_i3c_bfm | MIPI I3C bus functional model and agent | planned | FPGA + ASIC | Hard |
| of_vip_spi_mon | SPI monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_spi_bfm | SPI bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_xspi_mon | Quad/Octal SPI (xSPI) monitor and protocol checker | simulated | FPGA + ASIC | Medium |
| of_vip_xspi_bfm | Quad/Octal SPI host agent and flash model | simulated | FPGA + ASIC | Medium |
| of_vip_uart_mon | UART monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_uart_bfm | UART bus functional model and agent | simulated | FPGA + ASIC | Easy |
automotive bus vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_can_mon | CAN / CAN FD / CAN XL monitor and protocol checker | simulated | FPGA + ASIC | Medium |
| of_vip_can_bfm | CAN / CAN FD / CAN XL bus functional model and agent | simulated | FPGA + ASIC | Medium |
| of_vip_lin_mon | LIN monitor and protocol checker | planned | FPGA + ASIC | Easy |
| of_vip_lin_bfm | LIN bus functional model and agent | planned | FPGA + ASIC | Easy |
| of_vip_flexray_mon | FlexRay monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_flexray_bfm | FlexRay bus functional model and agent | planned | FPGA + ASIC | Hard |
ethernet vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_eth_mii_mon | Ethernet MII/RMII/GMII/RGMII monitor and protocol checker | simulated | FPGA + ASIC | Medium |
| of_vip_eth_mii_bfm | Ethernet MII/RMII/GMII/RGMII bus functional model and agent | simulated | FPGA + ASIC | Medium |
| of_vip_eth_xgmii_mon | Ethernet XGMII/XLGMII/CGMII monitor and protocol checker | planned | FPGA + ASIC | Medium |
| of_vip_eth_xgmii_bfm | Ethernet XGMII/XLGMII/CGMII bus functional model and agent | planned | FPGA + ASIC | Medium |
| of_vip_eth_pkt_gen | Ethernet packet generator and checker | planned | FPGA + ASIC | Medium |
high-speed serial vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_usb2_mon | USB 2.0 monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_usb2_bfm | USB 2.0 bus functional model and agent | planned | FPGA + ASIC | Hard |
| of_vip_usb3_mon | USB 3.2 monitor and protocol checker | planned | FPGA + ASIC | Very hard |
| of_vip_usb3_bfm | USB 3.2 bus functional model and agent | planned | FPGA + ASIC | Very hard |
| of_vip_usb4_mon | USB4 monitor and protocol checker | planned | FPGA + ASIC | Very hard |
| of_vip_usb4_bfm | USB4 bus functional model and agent | planned | FPGA + ASIC | Very hard |
| of_vip_pcie_mon | PCI Express monitor and protocol checker | planned | FPGA + ASIC | Very hard |
| of_vip_pcie_bfm | PCI Express bus functional model and agent | planned | FPGA + ASIC | Very hard |
| of_vip_cxl_mon | CXL monitor and protocol checker | planned | FPGA + ASIC | Very hard |
| of_vip_cxl_bfm | CXL bus functional model and agent | planned | FPGA + ASIC | Very hard |
memory interface vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_ddr4_mon | DDR4 monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_ddr4_bfm | DDR4 SDRAM memory model | planned | FPGA + ASIC | Hard |
| of_vip_ddr5_mon | DDR5 monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_ddr5_bfm | DDR5 SDRAM and DIMM memory model | planned | FPGA + ASIC | Hard |
| of_vip_lpddr_mon | LPDDR4/LPDDR5 monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_lpddr_bfm | LPDDR4/LPDDR5 memory model | planned | FPGA + ASIC | Hard |
| of_vip_hbm_mon | HBM monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_hbm_bfm | HBM memory model | planned | FPGA + ASIC | Hard |
| of_vip_onfi_model | ONFI NAND flash model | planned | FPGA + ASIC | Medium |
mipi vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_csi2_mon | MIPI CSI-2 monitor and protocol checker | planned | FPGA + ASIC | Medium |
| of_vip_csi2_bfm | MIPI CSI-2 camera model and agent | planned | FPGA + ASIC | Medium |
| of_vip_dsi_mon | MIPI DSI monitor and protocol checker | planned | FPGA + ASIC | Medium |
| of_vip_dsi_bfm | MIPI DSI bus functional model and agent | planned | FPGA + ASIC | Medium |
| of_vip_dphy_mon | MIPI D-PHY monitor and checker | planned | FPGA + ASIC | Hard |
| of_vip_cphy_mon | MIPI C-PHY monitor and checker | planned | FPGA + ASIC | Hard |
display vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_hdmi_mon | HDMI monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_hdmi_bfm | HDMI bus functional model and agent | planned | FPGA + ASIC | Hard |
| of_vip_dp_mon | DisplayPort monitor and protocol checker | planned | FPGA + ASIC | Hard |
| of_vip_dp_bfm | DisplayPort bus functional model and agent | planned | FPGA + ASIC | Hard |
storage vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_sd_emmc_mon | SD / eMMC monitor and protocol checker | planned | FPGA + ASIC | Medium |
| of_vip_sd_emmc_bfm | SD card and eMMC device model | planned | FPGA + ASIC | Medium |
| of_vip_ufs_mon | UFS monitor and protocol checker | planned | FPGA + ASIC | Very hard |
| of_vip_ufs_bfm | UFS bus functional model and agent | planned | FPGA + ASIC | Very hard |
| of_vip_nvme_host | NVMe host agent and device model | planned | FPGA + ASIC | Hard |
debug interface vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_jtag_mon | JTAG monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_jtag_bfm | JTAG bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_swd_mon | Serial Wire Debug monitor and protocol checker | planned | FPGA + ASIC | Easy |
| of_vip_swd_bfm | Serial Wire Debug bus functional model and agent | planned | FPGA + ASIC | Easy |
die-to-die vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_ucie_mon | UCIe monitor and protocol checker | planned | FPGA + ASIC | Very hard |
| of_vip_ucie_bfm | UCIe bus functional model and agent | planned | FPGA + ASIC | Very hard |
| of_vip_jesd204_mon | JESD204B/C link monitor and agent | planned | FPGA + ASIC | Hard |
open bus vip
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_wb_mon | Wishbone monitor and protocol checker | simulated | FPGA + ASIC | Easy |
| of_vip_wb_bfm | Wishbone bus functional model and agent | simulated | FPGA + ASIC | Easy |
| of_vip_tilelink_mon | TileLink monitor and protocol checker | planned | FPGA + ASIC | Medium |
| of_vip_tilelink_bfm | TileLink bus functional model and agent | planned | FPGA + ASIC | Medium |
| of_vip_obi_mon | OBI monitor and protocol checker | planned | FPGA + ASIC | Easy |
| of_vip_obi_bfm | OBI bus functional model and agent | planned | FPGA + ASIC | Easy |
verification infrastructure
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_vip_scoreboard | Transaction scoreboard | simulated | FPGA + ASIC | Easy |
| of_vip_coverage | Functional coverage collector | simulated | FPGA + ASIC | Medium |
| of_vip_mem_model | Sparse memory model | simulated | FPGA + ASIC | Easy |
| of_vip_clk_rst_gen | Clock and reset generator | simulated | FPGA + ASIC | Easy |
| of_vip_ral_gen | Register model generator | simulated | FPGA + ASIC | Medium |
| of_vip_irq_mon | Interrupt monitor | planned | FPGA + ASIC | Easy |
| of_vip_gpio_agent | GPIO pin agent | planned | FPGA + ASIC | Easy |
| of_vip_stream_tg | Stream traffic generator and checker | simulated | FPGA + ASIC | Easy |
| of_vip_cdc_assert | CDC and reset assertion library | planned | FPGA + ASIC | Medium |
| of_vip_power_aware | Power-aware checker | planned | FPGA + ASIC | Hard |
| of_vip_formal_props | Bus protocol formal property sets | simulated | FPGA + ASIC | Medium |
| of_vip_rnm_stim | Real-number analog stimulus models | planned | FPGA + ASIC | Medium |
| of_vip_ref_model_bridge | Reference model bridge | planned | FPGA + ASIC | Easy |
| of_vip_riscv_tracer | RISC-V instruction trace checker | planned | FPGA + ASIC | Medium |