IP PortfolioVerification IPmemory interface vip
of_vip_ddr4_mon
DDR4 monitor and protocol checker
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
DDR4 monitor decoding commands per rank and bank and checking JEDEC timing (tRCD, tRP, tRAS, tFAW, tRFC and others), mode register settings and refresh rate.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 120 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- JEDEC JESD79-4
More in memory interface vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_ddr4_bfm | DDR4 SDRAM memory model | planned |
| of_vip_ddr5_mon | DDR5 monitor and protocol checker | planned |
| of_vip_ddr5_bfm | DDR5 SDRAM and DIMM memory model | planned |
| of_vip_lpddr_mon | LPDDR4/LPDDR5 monitor and protocol checker | planned |
| of_vip_lpddr_bfm | LPDDR4/LPDDR5 memory model | planned |
| of_vip_hbm_mon | HBM monitor and protocol checker | planned |
| of_vip_hbm_bfm | HBM memory model | planned |
| of_vip_onfi_model | ONFI NAND flash model | planned |