IP PortfolioVerification IPserial peripheral vip
of_vip_i3c_mon
MIPI I3C monitor and protocol checker
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
I3C monitor decoding SDR and HDR-DDR frames, CCCs, dynamic address assignment and in-band interrupts, with timing and parity checks.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 2 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- MIPI I3C
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|---|---|---|
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| of_vip_i2c_bfm | I2C bus functional model and agent | simulated |
| of_vip_i3c_bfm | MIPI I3C bus functional model and agent | planned |
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| of_vip_spi_bfm | SPI bus functional model and agent | simulated |
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| of_vip_uart_mon | UART monitor and protocol checker | simulated |
| of_vip_uart_bfm | UART bus functional model and agent | simulated |