IP PortfolioVerification IPopen bus vip
of_vip_wb_mon
Wishbone monitor and protocol checker
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Wishbone B4 classic and pipelined monitor checking CYC/STB/ACK/ERR/RTY handshakes, STALL behavior and registered feedback burst cycles.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 112 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- Wishbone B4
More in open bus vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_wb_bfm | Wishbone bus functional model and agent | simulated |
| of_vip_tilelink_mon | TileLink monitor and protocol checker | planned |
| of_vip_tilelink_bfm | TileLink bus functional model and agent | planned |
| of_vip_obi_mon | OBI monitor and protocol checker | planned |
| of_vip_obi_bfm | OBI bus functional model and agent | planned |