IP PortfolioAnalog and mixed-signalclocking
of_ams_jitter_cleaner
Jitter attenuator PLL
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
Dual-loop PLL with a narrow-bandwidth first loop and low-noise second loop that cleans recovered or system clocks for SerDes and data converter sampling.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| refclk | in | clock | 1 | |
| clkout | out | clock | 4 | |
| lock | out | serial | 1 |
Standards
- ITU-T G.8262
More in clocking
| ID | Block | Maturity |
|---|---|---|
| of_ams_pll_intn | Integer-N charge-pump PLL | planned |
| of_ams_pll_fracn | Fractional-N PLL with delta-sigma modulator | planned |
| of_ams_adpll | All-digital PLL | planned |
| of_ams_vco_ring | Ring voltage-controlled oscillator | planned |
| of_ams_vco_lc | LC voltage-controlled oscillator | planned |
| of_ams_dll | Delay-locked loop | planned |
| of_ams_cdr | Clock and data recovery | planned |
| of_ams_xo | Crystal oscillator driver | planned |
| of_ams_xo_32k | 32.768 kHz low-power crystal oscillator | planned |
| of_ams_rcosc | Trimmed RC oscillator | planned |