IP PortfolioDatapath and DSPstorage helpers
of_delay_line
Shift-register delay line
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
WIDTH-bit shift-register delay line of DELAY stages with clock enable and all intermediate taps; optional reset (RESET=0 lets FPGA tools map it to SRL shift registers).
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | parallel | 16 | |
| m_out | out | parallel | 16 |
Standards
No external standard applies.
More in storage helpers
| ID | Block | Maturity |
|---|---|---|
| of_fifo_sync | Synchronous FIFO | fpga-routed |
| of_fifo_async | Asynchronous (dual-clock) FIFO | simulated |
| of_lifo | Synchronous stack (LIFO) | simulated |
| of_regfile | Multi-port register file | simulated |
| of_cam | Content-addressable memory (flop-based) | fpga-routed |
| of_tcam | Ternary CAM (logic based) | planned |
| of_pingpong | Ping-pong (double) buffer | planned |
| of_line_buffer | Image line buffer | planned |
| of_fifo_packet | Packet FIFO with commit and drop | simulated |
| of_queue_mgr | Multi-queue shared buffer manager | planned |