IP PortfolioDatapath and DSPstorage helpers
of_fifo_sync
Synchronous FIFO
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
Single-clock FIFO of any depth >= 2 with standard (registered read) or first-word-fall-through output, programmable almost-full / almost-empty thresholds, occupancy count, overflow / underflow pulses and synchronous flush.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | valid-qualified bus | 32 | |
| m_out | out | valid-qualified bus | 32 |
Standards
No external standard applies.
More in storage helpers
| ID | Block | Maturity |
|---|---|---|
| of_fifo_async | Asynchronous (dual-clock) FIFO | simulated |
| of_lifo | Synchronous stack (LIFO) | simulated |
| of_regfile | Multi-port register file | simulated |
| of_cam | Content-addressable memory (flop-based) | fpga-routed |
| of_delay_line | Shift-register delay line | simulated |
| of_tcam | Ternary CAM (logic based) | planned |
| of_pingpong | Ping-pong (double) buffer | planned |
| of_line_buffer | Image line buffer | planned |
| of_fifo_packet | Packet FIFO with commit and drop | simulated |
| of_queue_mgr | Multi-queue shared buffer manager | planned |