IP PortfolioDatapath and DSPstorage helpers
of_fifo_async
Asynchronous (dual-clock) FIFO
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Dual-clock FIFO for clock-domain crossing. Gray-coded read/write pointers cross through 2-4 flop synchronizers; registered, conservative full/empty flags; per-domain occupancy counts and almost-full / almost-empty; standard or first-word-fall-through read.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | valid-qualified bus | 32 | |
| m_out | out | valid-qualified bus | 32 | |
| rd_clk | in | clock | 1 |
Standards
No external standard applies.
More in storage helpers
| ID | Block | Maturity |
|---|---|---|
| of_fifo_sync | Synchronous FIFO | fpga-routed |
| of_lifo | Synchronous stack (LIFO) | simulated |
| of_regfile | Multi-port register file | simulated |
| of_cam | Content-addressable memory (flop-based) | fpga-routed |
| of_delay_line | Shift-register delay line | simulated |
| of_tcam | Ternary CAM (logic based) | planned |
| of_pingpong | Ping-pong (double) buffer | planned |
| of_line_buffer | Image line buffer | planned |
| of_fifo_packet | Packet FIFO with commit and drop | simulated |
| of_queue_mgr | Multi-queue shared buffer manager | planned |