IP PortfolioDatapath and DSPfloating point
of_posit_unit
Posit arithmetic unit
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Posit add, multiply, divide and conversion to and from IEEE 754 for parametric posit width and exponent size, with an optional quire accumulator.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| opnd | in | valid-qualified bus | 64 | |
| y | out | valid-qualified bus | 32 |
Standards
- Posit Standard 2022
More in floating point
| ID | Block | Maturity |
|---|---|---|
| of_fp_add | Floating-point adder/subtractor | simulated |
| of_fp_mul | Floating-point multiplier | simulated |
| of_fp_round | Floating-point round & pack unit | simulated |
| of_fp2int | Floating-point to fixed-point converter | simulated |
| of_int2fp | Fixed-point to floating-point converter | simulated |
| of_fp_fma | Floating-point fused multiply-add | simulated |
| of_fp_divsqrt | Floating-point divide and square root | simulated |
| of_fp_cmp | Floating-point compare, min/max and classify | simulated |
| of_fp_cvt | Floating-point format converter | simulated |
| of_bf16_dotp | bfloat16 dot-product unit | simulated |