IP PortfolioInterface controllerscamera
of_csi2_rx
MIPI CSI-2 receiver
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
MIPI CSI-2 receiver with 1 to 8 lanes over D-PHY or C-PHY PPI, virtual channel and data type demultiplexing, ECC/CRC checking and RAW/YUV/RGB unpacking.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| ppi_rx | in | parallel | 64 | |
| pixels | out | AXI4-Stream | 64 |
Standards
- MIPI CSI-2 v4.0
More in camera
| ID | Block | Maturity |
|---|---|---|
| of_csi2_tx | MIPI CSI-2 transmitter | planned |
| of_slvs_ec_rx | SLVS-EC link layer receiver | planned |
| of_dvp_camera | Parallel camera interface (DVP) | planned |