IP PortfolioInterface controllerscamera
of_dvp_camera
Parallel camera interface (DVP)
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
8 to 16 bit parallel camera input with HSYNC/VSYNC or BT.656 embedded sync, cropping and AXI-Stream video output.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | parallel | 16 | |
| sync_in | in | parallel | 2 | |
| pclk_in | in | clock | 1 | |
| pixels | out | AXI4-Stream | 16 |
Standards
- ITU-R BT.656-5
More in camera
| ID | Block | Maturity |
|---|---|---|
| of_csi2_rx | MIPI CSI-2 receiver | planned |
| of_csi2_tx | MIPI CSI-2 transmitter | planned |
| of_slvs_ec_rx | SLVS-EC link layer receiver | planned |