IP PortfolioInterface controllerscamera
of_csi2_tx
MIPI CSI-2 transmitter
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
MIPI CSI-2 transmitter for image sensors, ISPs and bridges with packet assembly, virtual channels, line and frame sync and D-PHY PPI output.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pixels | in | AXI4-Stream | 64 | |
| ppi_tx | out | parallel | 64 |
Standards
- MIPI CSI-2 v4.0
More in camera
| ID | Block | Maturity |
|---|---|---|
| of_csi2_rx | MIPI CSI-2 receiver | planned |
| of_slvs_ec_rx | SLVS-EC link layer receiver | planned |
| of_dvp_camera | Parallel camera interface (DVP) | planned |