IP PortfolioInterface controllersethernet_mac
of_eth_mac_100g
40G/50G/100G Ethernet MAC and PCS
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Multi-lane MAC and PCS for 40G, 50G and 100G with lane alignment markers, deskew, Clause 91 RS(528,514) and RS(544,514) FEC and 4x25G or 2x50G PAM4 lane mapping.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| serdes_tx | out | parallel | 256 | |
| serdes_rx | in | parallel | 256 | |
| tx | in | AXI4-Stream | 512 | |
| rx | out | AXI4-Stream | 512 |
Standards
- IEEE 802.3ba-2010
- IEEE 802.3bj-2014
- IEEE 802.3cd-2018
More in ethernet_mac
| ID | Block | Maturity |
|---|---|---|
| of_eth_mac_1g | 1G Ethernet MAC | simulated |
| of_eth_mac_10g | 10G Ethernet MAC and 10GBASE-R PCS | planned |
| of_eth_mac_25g | 25G Ethernet MAC, PCS and RS-FEC | planned |
| of_eth_mac_400g | 200G/400G Ethernet MAC and PCS | planned |
| of_eth_mac_800g | 800G Ethernet MAC and PCS | planned |