IP PortfolioInterface controllersethernet_mac
of_eth_mac_800g
800G Ethernet MAC and PCS
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
800GBASE-R MAC and PCS built from two 400G FEC flows with 8x100G or 4x200G PAM4 lane options.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pma_tx | out | parallel | 2048 | |
| pma_rx | in | parallel | 2048 | |
| tx | in | AXI4-Stream | 2048 | |
| rx | out | AXI4-Stream | 2048 |
Standards
- IEEE 802.3df-2024
More in ethernet_mac
| ID | Block | Maturity |
|---|---|---|
| of_eth_mac_1g | 1G Ethernet MAC | simulated |
| of_eth_mac_10g | 10G Ethernet MAC and 10GBASE-R PCS | planned |
| of_eth_mac_25g | 25G Ethernet MAC, PCS and RS-FEC | planned |
| of_eth_mac_100g | 40G/50G/100G Ethernet MAC and PCS | planned |
| of_eth_mac_400g | 200G/400G Ethernet MAC and PCS | planned |