IP PortfolioInterface controllersethernet_mac
of_eth_mac_1g
1G Ethernet MAC
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
10/100/1000 Mbit/s Ethernet MAC with MII, GMII and RGMII interfaces, FCS insertion and checking, pause frames, VLAN tagging and statistics counters.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| gmii_tx | out | parallel | 10 | |
| gmii_rx | in | parallel | 10 | |
| tx | in | AXI4-Stream | 8 | |
| rx | out | AXI4-Stream | 8 |
Standards
- IEEE 802.3-2022
Basis projects
Permissive open projects the implementation may build on.
- verilog-ethernet (MIT)
- LiteEth (BSD-2-Clause)
More in ethernet_mac
| ID | Block | Maturity |
|---|---|---|
| of_eth_mac_10g | 10G Ethernet MAC and 10GBASE-R PCS | planned |
| of_eth_mac_25g | 25G Ethernet MAC, PCS and RS-FEC | planned |
| of_eth_mac_100g | 40G/50G/100G Ethernet MAC and PCS | planned |
| of_eth_mac_400g | 200G/400G Ethernet MAC and PCS | planned |
| of_eth_mac_800g | 800G Ethernet MAC and PCS | planned |