IP PortfolioInterface PHYsmemory_phy
of_ddr5_phy
DDR5 PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 1
DDR5 PHY with DFI 5.0 interface, two 40-bit subchannels, DFE-aware read training, duty-cycle adjustment and support for RDIMM and MRDIMM data rates.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| dq | inout | parallel | 80 | |
| dqs | inout | differential pair | 10 | |
| ck | out | differential pair | 1 | |
| ca | out | parallel | 14 | |
| dfi_wr | in | parallel | 320 | |
| dfi_rd | out | parallel | 320 | |
| dfi_cmd | in | parallel | 64 |
Standards
- JEDEC JESD79-5
- DFI 5.0
Notes
Pairs with of_ddr5_ctrl and of_ddr5_mrdimm_ctrl; the Dyber, Inc. bridge die uses this as its DIMM-side interface.
More in memory_phy
| ID | Block | Maturity |
|---|---|---|
| of_ddr4_phy | DDR3/DDR4 PHY | planned |
| of_lpddr4_phy | LPDDR4/LPDDR4X PHY | planned |
| of_lpddr5_phy | LPDDR5/LPDDR5X PHY | planned |
| of_lpddr6_phy | LPDDR6 PHY | planned |
| of_gddr6_phy | GDDR6 PHY | planned |
| of_gddr7_phy | GDDR7 PHY | planned |
| of_hbm2e_phy | HBM2E PHY | planned |
| of_hbm3_phy | HBM3/HBM3E PHY | planned |
| of_hbm4_phy | HBM4 PHY | planned |
| of_onfi_phy | ONFI / Toggle NAND PHY | planned |