IP PortfolioInterface PHYsmemory_phy
of_ddr4_phy
DDR3/DDR4 PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 1
DDR3, DDR3L and DDR4 PHY with DFI 4.0 interface, per-bit deskew, read and write leveling, gate training, VREF training and ZQ calibrated drivers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| dq | inout | parallel | 72 | |
| dqs | inout | differential pair | 9 | |
| ck | out | differential pair | 1 | |
| ca | out | parallel | 14 | |
| dfi_wr | in | parallel | 288 | |
| dfi_rd | out | parallel | 288 | |
| dfi_cmd | in | parallel | 64 |
Standards
- JEDEC JESD79-3
- JEDEC JESD79-4
- DFI 4.0
More in memory_phy
| ID | Block | Maturity |
|---|---|---|
| of_ddr5_phy | DDR5 PHY | planned |
| of_lpddr4_phy | LPDDR4/LPDDR4X PHY | planned |
| of_lpddr5_phy | LPDDR5/LPDDR5X PHY | planned |
| of_lpddr6_phy | LPDDR6 PHY | planned |
| of_gddr6_phy | GDDR6 PHY | planned |
| of_gddr7_phy | GDDR7 PHY | planned |
| of_hbm2e_phy | HBM2E PHY | planned |
| of_hbm3_phy | HBM3/HBM3E PHY | planned |
| of_hbm4_phy | HBM4 PHY | planned |
| of_onfi_phy | ONFI / Toggle NAND PHY | planned |