IP PortfolioInterface PHYsmemory_phy
of_gddr7_phy
GDDR7 PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
GDDR7 PHY with PAM3 transmit and receive, WCK clocking, link training and calibration for four channels per device.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| dq | inout | parallel | 32 | |
| dqs | inout | differential pair | 4 | |
| ck | out | differential pair | 1 | |
| ca | out | parallel | 14 | |
| dfi_wr | in | parallel | 128 | |
| dfi_rd | out | parallel | 128 | |
| dfi_cmd | in | parallel | 64 | |
| wck | out | differential pair | 4 |
Standards
- JEDEC JESD239
More in memory_phy
| ID | Block | Maturity |
|---|---|---|
| of_ddr4_phy | DDR3/DDR4 PHY | planned |
| of_ddr5_phy | DDR5 PHY | planned |
| of_lpddr4_phy | LPDDR4/LPDDR4X PHY | planned |
| of_lpddr5_phy | LPDDR5/LPDDR5X PHY | planned |
| of_lpddr6_phy | LPDDR6 PHY | planned |
| of_gddr6_phy | GDDR6 PHY | planned |
| of_hbm2e_phy | HBM2E PHY | planned |
| of_hbm3_phy | HBM3/HBM3E PHY | planned |
| of_hbm4_phy | HBM4 PHY | planned |
| of_onfi_phy | ONFI / Toggle NAND PHY | planned |