IP PortfolioInterface PHYslvds_io
of_mlvds_io
M-LVDS multipoint transceiver
Maturity plannedTargets ASIC (CMOS) onlyDifficulty MediumPriority 3
Multipoint LVDS bus transceiver with Type 1 and Type 2 receivers for backplane clock and data distribution.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| bus | inout | differential pair | 1 | |
| txd | in | serial | 1 | |
| rxd | out | serial | 1 | |
| de | in | serial | 1 |
Standards
- TIA/EIA-899
More in lvds_io
| ID | Block | Maturity |
|---|---|---|
| of_lvds_serdes | Source-synchronous LVDS SerDes | planned |
| of_slvs400_io | SLVS-400 I/O | planned |
| of_sublvds_rx | Sub-LVDS receiver | planned |
| of_fpdlink_tx_phy | 7:1 LVDS display serializer PHY | planned |
| of_sgmii_lvds_phy | SGMII over LVDS PHY | planned |