IP PortfolioInterface PHYslvds_io
of_lvds_serdes
Source-synchronous LVDS SerDes
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 1
Multi-lane source-synchronous LVDS interface with 1:N serializer and deserializer, per-lane delay lines, bitslip word alignment and clock forwarding, for ADC, sensor and board links up to about 1.6 Gb/s per pair.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| txd | out | differential pair | 4 | |
| rxd | in | differential pair | 4 | |
| par_tx | in | parallel | 32 | |
| par_rx | out | parallel | 32 |
Standards
- TIA/EIA-644-A
Notes
Builds on the LVDS pad cells of_io_lvds (foundation_physical).
More in lvds_io
| ID | Block | Maturity |
|---|---|---|
| of_slvs400_io | SLVS-400 I/O | planned |
| of_sublvds_rx | Sub-LVDS receiver | planned |
| of_mlvds_io | M-LVDS multipoint transceiver | planned |
| of_fpdlink_tx_phy | 7:1 LVDS display serializer PHY | planned |
| of_sgmii_lvds_phy | SGMII over LVDS PHY | planned |