IP PortfolioInterface PHYslvds_io
of_sgmii_lvds_phy
SGMII over LVDS PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
1.25 Gb/s SGMII and 1000BASE-X PHY built on LVDS I/O with oversampling data recovery, avoiding a full SerDes for gigabit Ethernet.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| txd | out | differential pair | 1 | |
| rxd | in | differential pair | 1 | |
| tbi_tx | in | parallel | 10 | |
| tbi_rx | out | parallel | 10 |
Standards
- Cisco SGMII 1.8
- IEEE 802.3-2022
More in lvds_io
| ID | Block | Maturity |
|---|---|---|
| of_lvds_serdes | Source-synchronous LVDS SerDes | planned |
| of_slvs400_io | SLVS-400 I/O | planned |
| of_sublvds_rx | Sub-LVDS receiver | planned |
| of_mlvds_io | M-LVDS multipoint transceiver | planned |
| of_fpdlink_tx_phy | 7:1 LVDS display serializer PHY | planned |