IP PortfolioInterface PHYsusb_phy
of_usb_fs_xcvr
USB full-speed transceiver
Maturity plannedTargets ASIC (CMOS) onlyDifficulty MediumPriority 1
USB 2.0 full/low-speed transceiver with single-ended receivers, differential receiver, slew-controlled driver and switchable 1.5 kOhm pull-up.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| dp | inout | analog | 1 | |
| dm | inout | analog | 1 | |
| txd | in | parallel | 3 | |
| rxd | out | parallel | 3 |
Standards
- USB 2.0
More in usb_phy
| ID | Block | Maturity |
|---|---|---|
| of_usb2_phy | USB 2.0 PHY (UTMI+) | planned |
| of_eusb2_phy | eUSB2 PHY | planned |
| of_usb3_phy | USB 3.2 PHY | planned |
| of_usb4_phy | USB4 PHY | planned |
| of_typec_combo_phy | USB-C combo PHY (USB 3.2 + DisplayPort) | planned |