of_cpu_fpu_multiformat
Multi-format pipelined FPU
Maturity simulatedTargets FPGA + ASICDifficulty HardPriority 1
Pipelined FMA-based FPU supporting FP64, FP32, FP16, BF16 and FP8 with packed SIMD variants, division and square root, configurable per format.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| op | in | valid-qualified bus | 200 | |
| res | out | valid-qualified bus | 64 |
Standards
- IEEE 754-2019
- RISC-V F
- RISC-V D
- RISC-V Zfh
Basis projects
Permissive open projects the implementation may build on.
- CVFPU / FPnew (OpenHW Group, PULP) (SHL-0.51)
More in fpu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_fpu_compact | Area-optimised iterative FPU | planned |