of_cpu_xif_adapter
CORE-V eXtension Interface adapter
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Coprocessor attachment port implementing the CORE-V eXtension Interface so custom functional units can be added without modifying the core pipeline.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| issue | out | valid-qualified bus | 64 | |
| result | in | valid-qualified bus | 64 |
Standards
- OpenHW CORE-V-XIF
More in isa_ext
| ID | Block | Maturity |
|---|---|---|
| of_cpu_ext_bitmanip | Bit-manipulation extension unit | simulated |
| of_cpu_ext_scalar_crypto | Scalar cryptography extension unit | simulated |
| of_cpu_ext_vector_crypto | Vector cryptography extension unit | planned |
| of_cpu_ext_packed_simd | Packed SIMD extension unit | planned |
| of_cpu_ext_matrix | Matrix extension unit | planned |
| of_cpu_ext_dot_product | Packed dot-product extension | planned |
| of_cpu_ext_dsp_hwloop | Hardware loop and addressing extension | planned |
| of_cpu_ext_cfi | Control-flow integrity extension unit | planned |