IP PortfolioProcessorsriscv_secure
of_cpu_rv32_secure
Security-hardened RV32 core
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
RV32IMC core with Smepmp, data-independent timing, dual-core or shadow-register redundancy, instruction integrity checks and dummy instruction insertion.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| alert_out | out | parallel | 2 |
Standards
- RISC-V RV32IMC
- RISC-V Smepmp 1.0
- RISC-V Zkt
Basis projects
Permissive open projects the implementation may build on.
- Ibex (lowRISC) (Apache-2.0)
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_secure
| ID | Block | Maturity |
|---|---|---|
| of_cpu_cheriot_mcu | CHERIoT capability microcontroller core | planned |
| of_cpu_rv64_cheri | CHERI RV64 application core | planned |
| of_cpu_world_isolation | Hardware world isolation checker | planned |