IP PortfolioProcessorsriscv_secure
of_cpu_world_isolation
Hardware world isolation checker
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
World-identifier tagging of bus masters and memory-side checkers that partition memory and peripherals between trusted and untrusted execution environments.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| req | in | valid-qualified bus | 72 | |
| deny | out | valid-qualified bus | 8 |
Standards
No external standard applies.
Notes
Follows the WorldGuard model contributed to RISC-V International; no ratified specification yet.
More in riscv_secure
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32_secure | Security-hardened RV32 core | planned |
| of_cpu_cheriot_mcu | CHERIoT capability microcontroller core | planned |
| of_cpu_rv64_cheri | CHERI RV64 application core | planned |