IP PortfolioProcessorsriscv_app
of_cpu_rv64_dual_issue
RV64GC dual-issue in-order core
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Eight-stage dual-issue in-order RV64GC core with branch prediction, Sv39/Sv48 MMU and coherent L1 caches for efficiency-oriented application clusters.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RV64GC
- RISC-V Privileged 1.12
- RISC-V Sv48
- RISC-V Debug 0.13
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_app
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv64_inorder | RV64GC single-issue application core | planned |