IP PortfolioProcessorsriscv_app
of_cpu_rv64_inorder
RV64GC single-issue application core
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Six-stage single-issue in-order RV64GC core with Sv39 MMU, instruction and data caches and machine, supervisor and user modes, able to boot Linux.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RV64GC
- RISC-V Privileged 1.12
- RISC-V Sv39
- RISC-V Debug 0.13
Basis projects
Permissive open projects the implementation may build on.
- CVA6 (OpenHW Group) (SHL-0.51)
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_app
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv64_dual_issue | RV64GC dual-issue in-order core | planned |