of_sec_aes_gcm_siv
AES-GCM-SIV engine
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
Nonce-misuse-resistant AES-GCM-SIV with POLYVAL and per-nonce key derivation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| data_in | in | AXI4-Stream | 128 | |
| data_out | out | AXI4-Stream | 128 |
Standards
- NIST FIPS 197
- RFC 8452
More in aes
| ID | Block | Maturity |
|---|---|---|
| of_sec_aes_core | AES block cipher core | simulated |
| of_sec_aes_modes | AES modes engine | simulated |
| of_sec_aes_gcm | AES-GCM authenticated encryption engine | planned |
| of_sec_aes_xts | AES-XTS storage encryption engine | simulated |
| of_sec_aes_masked | Side-channel protected AES | planned |
| of_sec_aes_keywrap | AES key wrap engine | planned |