of_sec_key_vault
Key vault
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Key slot storage with per-slot usage policy, lock and clear, where keys move only between crypto engines and never to firmware.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| key_in | in | valid-qualified bus | 256 | |
| key_out | out | valid-qualified bus | 256 |
Standards
No external standard applies.
Basis projects
Permissive open projects the implementation may build on.
- Caliptra RTL (CHIPS Alliance) (Apache-2.0)
More in key_mgmt
| ID | Block | Maturity |
|---|---|---|
| of_sec_key_manager | Key manager | planned |
| of_sec_key_ladder | Content protection key ladder | planned |