IP PortfolioSecurityside_channel
of_sec_masking_gadgets
Masked logic gadget library
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Library of masked AND, XOR, refresh and register gadgets (DOM and HPC families) with parameterised order for building protected datapaths.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- ISO/IEC 17825
More in side_channel
| ID | Block | Maturity |
|---|---|---|
| of_sec_noise_gen | Power noise generator | planned |
| of_sec_rand_delay | Random delay and dummy operation inserter | planned |
| of_sec_dual_rail_lib | Dual-rail precharge logic cells | planned |
| of_sec_fault_detect | Crypto fault detection wrappers | planned |
| of_sec_iso_ldo | Crypto supply isolation regulator | planned |