IP PortfolioSecurityside_channel
of_sec_rand_delay
Random delay and dummy operation inserter
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
Clock-level jitter, random wait states and dummy rounds controlled by a randomness input to desynchronise side-channel traces.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| rnd_in | in | valid-qualified bus | 32 |
Standards
No external standard applies.
More in side_channel
| ID | Block | Maturity |
|---|---|---|
| of_sec_masking_gadgets | Masked logic gadget library | planned |
| of_sec_noise_gen | Power noise generator | planned |
| of_sec_dual_rail_lib | Dual-rail precharge logic cells | planned |
| of_sec_fault_detect | Crypto fault detection wrappers | planned |
| of_sec_iso_ldo | Crypto supply isolation regulator | planned |