IP PortfolioSensing and RFradar
of_radar_gpr
Ground-penetrating radar processor
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Stepped-frequency or impulse GPR acquisition control with background removal, gain and migration for subsurface imaging.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| raw | in | AXI4-Stream | 32 | |
| trace | out | AXI4-Stream | 32 |
Standards
No external standard applies.
More in radar
| ID | Block | Maturity |
|---|---|---|
| of_radar_fmcw_chirp_ctrl | FMCW chirp sequencer | simulated |
| of_radar_fe_24g | 24 GHz radar transceiver front end | planned |
| of_radar_fe_60g | 60 GHz radar transceiver front end | planned |
| of_radar_fe_77g | 76 to 81 GHz automotive radar front end | planned |
| of_radar_adc_frontend_dig | Radar IF digital front end | simulated |
| of_radar_range_fft | Range FFT engine | simulated |
| of_radar_doppler_fft | Doppler FFT engine | simulated |
| of_radar_cfar | CFAR detector (CA, OS, GO, SO) | simulated |
| of_radar_doa_bf | Direction-of-arrival beamforming estimator | planned |
| of_radar_doa_subspace | Subspace DOA engine (MUSIC, ESPRIT) | planned |