IP PortfolioSensing and RFrf_frontend
of_rf_frontend_ctrl
RF front end control interface
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Timed control word sequencer that drives switches, LNAs and PAs over MIPI RFFE or parallel GPIO at symbol boundaries.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| sclk | out | serial | 1 | |
| sdata | inout | serial | 1 |
Standards
- MIPI RFFE
More in rf_frontend
| ID | Block | Maturity |
|---|---|---|
| of_rf_lna | Low-noise amplifier family | planned |
| of_rf_pa | CMOS power amplifier | planned |
| of_rf_mixer | Mixer family | planned |
| of_rf_synth | RF frequency synthesizer | planned |
| of_rf_switch | RF switch (SPDT to SP8T) | planned |
| of_rf_phase_shifter | Digital phase shifter | planned |
| of_rf_attenuator | Digital step attenuator | planned |
| of_rf_vga | RF variable gain amplifier | planned |
| of_rf_power_detector | RF power detector | planned |
| of_rf_balun_match | Integrated balun and matching network library | planned |