IP PortfolioSensing and RFtime_frequency
of_time_ptp_gm
IEEE 1588 PTP grandmaster timing core
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Hardware timestamping, disciplined time-of-day counter, PPS input and output and servo assist for PTP grandmaster and boundary clocks.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pps_in | in | serial | 1 | |
| pps_out | out | serial | 1 | |
| tod | out | parallel | 80 |
Standards
- IEEE 1588-2019
- ITU-T G.8275.1
- IEEE 802.1AS
More in time_frequency
| ID | Block | Maturity |
|---|---|---|
| of_time_atomic_iface | Atomic clock disciplining interface | planned |
| of_time_csac_ctrl | Chip-scale atomic clock control loop | planned |
| of_time_synce | SyncE and frequency synchronizer | planned |