IP PortfolioSensing and RFtime_frequency
of_time_synce
SyncE and frequency synchronizer
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Recovered-clock selection, phase measurement and DPLL control for synchronous Ethernet equipment clocks.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| rclk | in | clock | 4 | |
| sysclk | out | clock | 1 |
Standards
- ITU-T G.8262
- ITU-T G.8264
More in time_frequency
| ID | Block | Maturity |
|---|---|---|
| of_time_ptp_gm | IEEE 1588 PTP grandmaster timing core | planned |
| of_time_atomic_iface | Atomic clock disciplining interface | planned |
| of_time_csac_ctrl | Chip-scale atomic clock control loop | planned |