IP PortfolioSensing and RFwireless_baseband

of_wl_mimo_detector

MIMO detector

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1

Linear MMSE and sphere-decoding style detection with soft LLR output for up to 4x4 or 8x8 spatial layers.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAXI4-Lite control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
re_ininAXI4-Stream128 
h_estinAXI4-Stream128 
llroutAXI4-Stream64 

Standards

  • 3GPP TS 38.211
  • IEEE 802.11ax

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