IP PortfolioSensing and RFwireless_baseband
of_wl_nr_chest
5G NR channel estimator
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
DM-RS based least-squares channel estimation with frequency and time interpolation and noise variance estimation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| re_in | in | AXI4-Stream | 32 | |
| h_est | out | AXI4-Stream | 64 |
Standards
- 3GPP TS 38.211
- 3GPP TS 38.214
More in wireless_baseband
| ID | Block | Maturity |
|---|---|---|
| of_wl_nr_ofdm_mod | 5G NR OFDM modulator | planned |
| of_wl_nr_ofdm_demod | 5G NR OFDM demodulator | planned |
| of_wl_mimo_detector | MIMO detector | planned |
| of_wl_nr_beam_mgmt | 5G NR beam management engine | planned |
| of_wl_nr_prach | 5G NR PRACH detector | planned |
| of_wl_nr_precoder | 5G NR layer mapper and precoder | planned |
| of_wl_lte_phy | LTE PHY baseband | planned |
| of_wl_nbiot_phy | NB-IoT and LTE-M PHY | planned |
| of_wl_wifi6_bb | Wi-Fi 6 baseband | planned |
| of_wl_wifi7_bb | Wi-Fi 7 baseband extensions | planned |