APB slave register block

Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1

AMBA APB4 slave register block with zero wait states, byte strobes and PSLVERR decode errors; the register map (RW, RO, W1C, W1P registers, reset values, writable masks) comes from a register-map specification (openforge.iplib.regmap).

FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	APB control bus	32	Control and status registers, including ID, VERSION and STATUS
hw_in	in	parallel	32
hw_out	out	parallel	32

Standards

AMBA APB4

More in register blocks

ID	Block	Maturity
of_regbank	Register bank core (register-map driven)	simulated
of_axil_regs	AXI4-Lite slave register block	simulated
of_wb_regs	Wishbone B4 slave register block	simulated