AXI4-Lite slave register block

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

AXI4-Lite slave register block with independent AW / W acceptance, registered B and R channels, byte strobes and SLVERR decode errors; the register map comes from a register-map specification (openforge.iplib.regmap).

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
hw_in	in	parallel	32
hw_out	out	parallel	32

Standards

AMBA AXI4-Lite

More in register blocks

ID	Block	Maturity
of_regbank	Register bank core (register-map driven)	simulated
of_apb_regs	APB slave register block	fpga-routed
of_wb_regs	Wishbone B4 slave register block	simulated