IP PortfolioSoC interconnectamba interconnect
of_chi_axi_bridge
CHI to AXI4 bridge
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Request node to AXI4 bridge that lets a CHI-based coherent mesh access AXI4 memory and peripherals, with transaction ID mapping and ordering.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| chi | in | valid-qualified bus | 512 | |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- AMBA CHI
- AMBA AXI4
More in amba interconnect
| ID | Block | Maturity |
|---|---|---|
| of_axil_xbar | AXI4-Lite crossbar | fpga-routed |
| of_axis_arb | AXI4-Stream packet arbiter / mux | simulated |
| of_axis_fifo | AXI4-Stream FIFO | simulated |
| of_axis_reg_slice | AXI4-Stream register slice | simulated |
| of_axis_width_conv | AXI4-Stream width converter | simulated |
| of_axi4_xbar | AXI4 crossbar | simulated |
| of_axi4_reg_slice | AXI4 register slice | simulated |
| of_axi4_width_conv | AXI4 data-width converter | simulated |
| of_axi4_id_remap | AXI4 ID width converter | planned |
| of_axi4_burst_split | AXI4 burst splitter | planned |