IP PortfolioSoC interconnectinterrupt controllers
of_clic
RISC-V CLIC
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Core-local interrupt controller with per-interrupt level, priority, edge/level trigger and vectoring, preemption and selective hardware vectoring.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| src | in | parallel | 64 | |
| irq_req | out | valid-qualified bus | 16 |
Standards
- RISC-V Core-Local Interrupt Controller (CLIC)
More in interrupt controllers
| ID | Block | Maturity |
|---|---|---|
| of_irq_agg | Interrupt aggregator | simulated |
| of_plic | RISC-V PLIC | simulated |
| of_aplic | RISC-V APLIC | planned |
| of_imsic | RISC-V IMSIC | planned |
| of_gic_style | GIC-style interrupt distributor | planned |